Previously, in manufacturing a semiconductor device by mounting a semiconductor chip on a wiring board, a wire bonding technique has been employed in which bonding pads on a semiconductor chip and leads on a wiring board are electrically connected by bonding via thin metal wires. Recently, in order to cope with a requirement for downsizing and lightening electrical equipments and an increase in the number of connection terminals of a semiconductor device, a flip chip mounting technology is employed in which a projecting electrode (hereinafter referred to as a “bump”), is formed on an electrode on a surface of a semiconductor chip and, then, the semiconductor chip is directly bonded to a wiring board in a face down manner.
In this flip chip mounting technology, bumps are formed on a plurality of electrodes formed on a semiconductor chip by using a metallic material such as solder and Au, these bumps and corresponding electrodes formed on a wiring board are positioned, and they are bonded by heat-press. In order to avoid destruction of bumps with a thermal stress caused by a difference in thermal expansion coefficients between the semiconductor chip and the wiring board during cooling after heat-press, an underfill material, which functions as a thermal stress buffer material, is supplied between the semiconductor chip and the wiring board.
Alternatively, a thermal stress caused by a difference in thermal expansion coefficients between a semiconductor chip and a wiring board during cooling after heat-press is buffered by using elastic bumps in place of underfill materials. For example, JP-A No. 1999-21447 and JP-A No. 2001-156091 disclose a structure in which a thermal stress is buffered by forming a cavity within a solder bump. JP-A No. 1999-233669 discloses a structure in which a thermal stress is buffered by utilizing elasticity of a resin by forming a bump consisting of a resin core made of a photo-sensitive resin such as polyimide, acrylic and the like and Ni plating and the like on a surface of the core. JP-A No. 2000-320148 discloses a structure in which a thermal stress generated between an integrated circuit and a mounting board is buffered by utilizing a U-shape elastic element at solder joints.
More recently, narrowing in wiring pitches as well as thinning and multilayering in semiconductor devices are accelerated, with depending on downsizing and performance enhancement in portable electronic equipments. In downsized, thinned or multilayered semiconductor devices, when a semiconductor chip is mounted on a wiring board by using the above conventional techniques to apply a pressure on the semiconductor chip or the wiring board, it is highly possible to break circuits formed thereon, affecting productivity and reliability of semiconductor devices. Especially when multilayer wiring boards are heat-pressed, low-k dielectric materials in multilayer wirings beneath electrode pads on a substrate or circuits of transistors and the like are frequently damaged, resulting in disorders in functions of semiconductor device.
Accordingly, for example, JP-A No. 2000-174165 discloses a structure in which a stress generated when a semiconductor chip is press bonded to a wiring board is buffered by forming a stress relaxation layer consisting of an epoxy resin under electrodes formed on the wiring board.
Alternatively, it is possible to reduce a pressure applied to a multilayer wiring beneath electrode pads on a substrate during bonding by using the above-mentioned bumps with a thermal stress buffering function and reducing its spring constant. However, in the previous bonding process, since a high pressure is applied during bonding, when a spring constant is low, it is possible that a pressure surpasses the elastic limit of the bump and, therefore, the bump cannot maintain its elasticity. Moreover, in the conventional bonding process, especially when a resin core-type bump is used, since bonding is carried out at a high temperature, a resin constituting a core deteriorates, causing a change in a spring constant.